Note: The job is a remote job and is open to candidates in USA. K2 Space Corporation is building the largest and highest-power satellites ever flown, and they are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package architecture and execution. This role focuses on flip-chip BGA and multi-chip module solutions, owning the end-to-end package strategy for high-performance mixed-signal and digital SoCs.

Responsibilities

• Own ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints
• Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability
• Define long-term packaging roadmap aligned with future ASIC nodes, bandwidth scaling, and multi-die integration
• Establish organizational package design standards, methodologies, and best practices
• Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content
• Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning
• Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces
• Own package-level SI/PI strategy, including high-speed digital interfaces (e.g., SerDes, JESD, Interlaken), power delivery network (PDN) design, and decoupling strategy
• Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling
• Serve as the primary technical interface to substrate vendors, assembly houses, and OSATs
• Drive material selection, substrate technology choices, and assembly process optimization

Skills

• Bachelor's degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field
• 10+ years of experience in ASIC package design, with deep expertise in FC-BGA
• Proven experience delivering high-pin-count, high-performance ASIC packages into production
• Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs
• Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS
• Experience working directly with OSATs and substrate vendors
• Knowledge of packaging qualification and test methodologies
• Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates)
• Background in high-speed digital or mixed-signal SoCs
• Familiarity with aerospace, space, or high-reliability electronics
• Experience defining packaging strategy from early architecture through first silicon and volume ramp
• Demonstrated history of building or scaling package design methodology within an organization

Benefits

• Equity in the company
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

Company Overview